A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that instance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
In order to increase the density of devices on an integrated circuit, the pitch of lines and other features is typically reduced. However, many lithography apparatus operate at or near their resolution limits. Various process techniques have been developed to enable features smaller than the minimum size imagable by a lithography apparatus to be created. For example, United States Patent Application Publication No. US 2003/0203320 discloses the use of conformal organic polymeric films to shrink gaps in a lithography pattern.
As another example, to etch lines narrower than the width of a line in resist, the exposed resist can be treated with an electron beam, causing the remaining resist to liquefy or plasticize and flow to partially close the exposed lines. Then, lines can be etched into the underlying substrate that are narrower than the lines printed in the resist. To expose lines at a pitch smaller than the minimum pitch imagable by the lithographic apparatus, double exposure techniques can be used—a first set of lines is imaged at double the desired pitch, then a second set, complementary to the first set, is imaged again at double the desired pitch but with a positional offset equal to the desired pitch. U.S. Pat. No. 6,589,713 discloses a method using both of these techniques to print features of reduced width and pitch.
A technique not using an e-beam to print spacer gate structures at high densities is disclosed in the article “Edge Defined Lithography for Nano-scale III-N Field Effect Transistors” by J P Long et al. (published in The International Conference on Compound Semiconductor Manufacturing Technology 2005 On-line Digest, available at http://www.gaasmantech.org/Digests/2005/index.htm, no 14.22). In this technique, a sacrificial polysilicon layer is patterned using conventional photolithographic techniques to form mesas and then a thin layer of Si3N4 is conformally deposited over the entire wafer. The Si3N4 layer is then etched using a highly anisotropic Reactive Ion Etching (RIE) process to leave thin Si3N4 walls either side of the polysilicon mesas. The mesas are then removed using a wet KOH etch to leave only the Si3N4 walls, which serve as masks during subsequent etching of SiO2 and polysilicon layers underneath the sacrificial polysilicon layer. The end result is thin polysilicon fins at twice the density of the mesas formed in the sacrificial polysilicon layer.
A similar technique is disclosed in “A Spacer Patterning Technology for Nanoscale CMOS” by Yang-Kyu Choi et al (published in IEEE Transactions on Electron Devices, Vol 49, No. 3, March 2002) to make silicon fins for FinFETS.
However, the disclosed techniques have limited application and may sometimes incorrectly image line-ends.